The present invention pertains to the field of computer systems. More particularly, the invention pertains to the field of detecting devices coupled to a hub interface in a computer system.
Prior computer systems typically rely on standardized busses, such as the Peripheral Component Interconnect (PCI) bus adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland Oregon, to allow computer system chipset components to communicate one with another. For example, a transaction originating at a processor and intended for a disk drive might first be delivered to a first chipset component that serves as an intermediary between the processor bus and a PCI bus. The first chipset component would then deliver the transaction over the PCI bus to a second system chipset component which would then deliver the transaction to the disk drive.
Busses such as the PCI bus also provide for communication with other computer system devices such as graphics controllers and network adapters. Because busses such as the PCI bus must interface with a variety of component types, each with varying requirements, the busses are not necessarily optimized for allowing communication between chipset components. Further, chipset manufacturers who rely on standardized busses such as the PCI bus must adhere to bus standards in order to ensure compatibility with other components, and are not at liberty to make substantial changes in how the chipset components communicate with each other.
Another issue that faces chipset component manufacturers in designing and manufacturing chipset components is the need to conform to standardized supply and signaling voltages when relying on busses such as PCI for communication between chipset components, thereby locking the manufacturers into certain design practices and manufacturing technologies. Therefore, it would be desirable to provide a flexible point to point interface that provides optimal communication between chipset components. In addition, it would be desirable to have a mechanism for initializing such an interface wherein the presence of a device coupled to the chipset via the interface is ascertained. Further, it would be advantageous to assign device identification numbers if a device is detected so that a processor may poll and read the devices.
According to one embodiment, a system is disclosed that includes a central processing unit (CPU) and a memory controller hub (MCH) coupled to the CPU. The MCH includes a first interface controller that is operable to detect the presence of a hub agent coupled to the MCH.